This apparatus is directed to an electron beam accessed random access memory which is capable of reading, writing and erasing information stored in a binary state. Such devices already appear in the literature. One such device is described by literature of the General Electric Company. Another such device is described in Applied Physics Letters, Volume 16, No. 147, (1970) by Hunert et al. That device and the one described by the General Electric Company have met with a measured degree of success. Nevertheless, the electron beam subjects the metal-oxide-semiconductor (MOS) memory dielectric layer in both devices to an excessive fluence of electrons over a period of time damaging the dielectric layer and destroying the ability of the MOS memory target to both store information and to read stored information. Over a period of time, obviously depending upon the electron beam current and the repetition of read and write cycles, the integral of the electron beam fluence ultimately produces an ionizing radiation damage in the silicon dioxide dielectric layer, causing physical damage to that layer evidenced in a saturation of positive charge which prohibits further reading, writing and erasing of information. Thus, the memory target life cycle of both prior art devices is severely limited.
The lifetime of data stored in the prior art devices is limited in that the charge stored in the silicon dioxide layer of the MOS target, prior to radiation damage, is volatile in that charges also accumulate during reading operations so that after a few readings, data storage is no longer distinguishable as a binary state, and must be erased and written again.
In addition the devices of the prior are somewhat limited in the number of bit storage locations per unit area. In the prior art devices, relatively thick layers of the MOS target must be penetrated by a highly accelerated electron beam, and therefore some scattering of the beam is produced as it traverses or penetrates into each successive target layer. Such scattering enlarges the definable storage area to an area larger than the optimum and results in the relative loose packing density of bit locations in a grid pattern organized on a semiconductor target used with an accelerating electron beam source of the sort taught heretofore. As a consequence, the packing density has been rather low and the useful life time has been shortened for the reasons mentioned above. This results in a device which is rather large and uneconomic to use in comparison with memory devices operative on entirely different techniques.
Furthermore, the source of electrons in the prior art devices are structures such as those used in Cathode Ray Tubes (CRT), with the result that the physical size and power requirement of the prior art devices are like that of a five inch CRT.
Also, the prior art devices are limited by the single CRT-like electron source, focus and beam deflection system to define a single information bit per access yielding a serial stream of bits. This sacrifices inherent speed and economy of multiple bit, parallel byte or word per access operation in reading, writing and erasing.
Also, the prior art requires about 18 times the electron beam current for operation, resulting in 350 times the electron beam power requirement.
In addition, the physical size and high vacuum requirement of the prior art (CRT-like equipment) limit the effective lifetime of the electron beam source, resulting in less economy of operation and periodic premature replacement.
Also, the prior art requires manufacturing steps which do not allow the economies of semiconductor-type batch manufacturing processes used to manufacture the present invention.
The devices of the prior art are further deficient in that they customarily use a junction diode as the output device. While the junction diode has a suitable diode gain, it is not anywhere near that attained by the electron beam penetration into a Schottky diode of the present device which has at least twice the gain. Accordingly, the output signal from this device is much larger and is easier to work with. This improves the accuracy of the data obtained from the memory device disclosed herein.
Furthermore, the prior art devices do not allow selective erase or overwrite of stored data of both polarities, and they must consequently resort to bulk or total erase of an entire storage array in order to erase previously written data, resulting in slow operation and higher cost of operation. The present invention allows selective overwrite or erase at the same rate as a normal reading cycle.
In comparison with semiconductor or core type random access memories, the cycle-time of the present invention is nearer the access time, and not large multiples of the access time thereby allowing greater speed and economy of operation.
Thus, the beam accessed storage devices of the prior art are capable of only a few reading and writing cycles and have a storage life shorter than other memories commercially acceptable, have less than optimum storage density, cannot selectively overwrite or erase data stored both polarities, are of large physical size, require much higher power for operation, produce only a single bit per random access and require multiple devices at multiplied power and space for parallel bit access, cannot be manufactured by economic semiconductor-type batch processes, resulting in limited utility and economy of operation.